1. Field of the Invention
The present invention relates to a decoding apparatus and a decoding method and, more particularly, to a decoding apparatus which functions as a bit stream decoding means in transmission and storage systems for compressed and non-compressed signals of sounds and images.
2. Description of the Prior Art
One example of a conventional decoding apparatus of this sort is shown in a block diagram of FIG. 1. As shown in FIG. 1, this conventional apparatus comprises a frame counter 31 for receiving a bit stream 101, a synchronous pattern detector 32, a data error check unit 33, a synchronous detector 34, and a frame error determination unit 35. FIG. 2 shows the structure of a unit frame of a bit stream to be decoded by this decoding apparatus. This unit frame consists of a synchronous pattern 201, data 202 and 204, and an error check pattern 203. The synchronous pattern 201 functions as a synchronous position detection pattern for maintaining frame synchronization. The data 202 and 204 are formed by compressing image data or sound data. The error check pattern 203 is used to check whether image data or sound data present in that unit frame has an error. Referring to FIG. 2, the data 204 of an immediately preceding unit frame connects to the synchronous pattern 201 of the next unit frame. In bit stream transmission, data encapsulated in these unit frames is continuously transmitted.
Referring to FIG. 1, the bit stream 101 with the frame structure shown in FIG. 2 is input at an input terminal 36 to the frame counter 31, the synchronous pattern detector 32, and the data error check unit 33. The synchronous pattern detector 32 detects the synchronous pattern 201 arranged at the head of the unit frame and outputs a synchronous pattern detection signal 104 to the frame counter 31 and the synchronous detector 34. Upon receiving this synchronous pattern detection signal 104, the frame counter 31 starts counting and performs the count operation for each unit frame of the input bit stream from the input terminal 36. Also, the frame counter 31 outputs a frame position signal 102 to the synchronous detector 34. If the timing of the frame position signal 102 transmitted to the synchronous detector 34 matches the timing of the synchronous pattern 201, which is contained in the synchronous pattern detection signal 104 and arranged at the head of the next unit frame, this indicates a normal synchronous state in which the synchronous pattern 201 in the unit frame is present in a normal synchronous position.
The synchronous detector 34 receives the frame position signal 102 supplied from the frame counter 31 and the synchronous pattern 201 in the next frame contained in the synchronous pattern detection signal 104 supplied from the synchronous pattern detector 32. If the timings of the frame position signal 102 and the synchronous pattern 201 in the next unit frame match each other, the synchronous detector 34 outputs a predetermined synchronous detection signal 103 to the frame counter 31 and the data error check unit 33. The frame counter 31 is initialized by this synchronous detection signal 103. Thereafter, as long as normal frames are continuously input, a series of synchronous detection operations as described above are repeatedly executed. If the timings of the frame position signal 102 and the synchronous pattern 201 in the next unit frame do not match each other, the synchronous detector 34 determines that some abnormality has occurred in the detection of the synchronous pattern, and outputs a synchronous detection error occurrence signal 106 to an external error processing circuit (not shown). The data error check unit 33 performs error check detection by referring to the error check pattern 203 in the unit frame of the bit stream. If an error is detected, the data error check unit 33 outputs a data error occurrence signal 105 to the frame error determination unit 35. When receiving this data error occurrence signal 105, the frame error determination unit 35 determines that an abnormality has occurred in the data in the frame, and outputs a frame error occurrence signal 107 to the error processing circuit (not shown).
In a normal decoding process, irrespective of whether the synchronous detection error occurrence signal 106 or the frame error occurrence signal 107 is output, it is determined that an abnormality has occurred in the data in the corresponding frame, and error processing is performed.
As a method of avoiding synchronous error detection for a bit stream input, a conventional technique proposed in Japanese Unexamined Patent Publication No. 60-246065 will be described next. In the method described in this proposal, if the synchronous signal has an error, another error detecting means locates and corrects the error. The gist of the contents of this conventional correction operation is as follows.
That is, an input synchronous signal from an input terminal is applied to a shift register by clocks. The shift register outputs the signal to a predetermined synchronous pattern coincidence circuit. If the synchronous signal has no error and exists in a correct position, an output terminal outputs a signal indicating that the synchronous signal is detected. Upon receiving the signal, a CRC arithmetic circuit is reset. Also, if data has no error, a CRC check terminal outputs a desired signal. An error flag signal is previously attached to the synchronous signal and applied from the input terminal to the shift register. If an error exists, correction processing is performed using the output from a circuit which is counting a signal in which the corresponding synchronous signal is detected. Therefore, if the synchronous signal pattern is entirely correct, synchronous detection can be performed only by using this pattern. If an error pattern with an error flag is present in a synchronous signal, detection is performed by taking account of the position from a CRC code. This prevents erroneous detection of a synchronous signal.
In the conventional decoding apparatus shown in FIG. 1, a synchronous signal is usually added to the head of a unit frame of a transmission bit stream, and a general approach is to allow the synchronous detector of the decoding apparatus to establish synchronization of that frame. However, if an error is generated in the synchronous signal due to, e.g., transmission, a synchronous error is produced by this error. Consequently, no frame decoding is performed, and error correction processing such as interpolation or muting is performed instead. This unavoidably degrades the quality of images and sounds.
Also, the following is a drawback of the method proposed in Japanese Unexamined Patent Publication No. 60-246065 in which in order to prevent synchronous error detection, an error flag is added to a synchronous signal, and the synchronous signal is corrected on the basis of an error position found by the error flag to thereby avoid synchronous error detection. That is, in the processing of particularly signal compression systems such as MPEG, the compression rate is improved by, e.g., decreasing the rate of a transmission system or reducing the storage capacity of a storage system. Consequently, it is practically very difficult to add redundant error detection data, which can locate an error position, to a transmission bit stream. Accordingly, one can only use a means of adding data capable of detecting only occurrence of an error. Under these circumstances, it is impossible to satisfactorily correct the synchronous signal position even with the application of the technique proposed in Japanese Unexamined Patent Publication No. 60-246065.